The present invention relates to a technique for fabricating a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique which is effective in its application to a wafer testing step, including a probe check.
According to studies made by the present inventor in connection with the fabrication of a semiconductor integrated circuit device, for example, it has been found that Japanese Unexamined Patent Publication Nos. Hei 5(1993)-343497 and 5(1993)-136219 disclose techniques associated with a wafer testing step, including a probe check.
For example, in the former publication No. Hei 5(1993)-343497, there is disclosed wafer inspection equipment provided with plural wafer inspection units and a cassette stock unit, wherein wafers stored in a predetermined cassette, out of plural cassettes stocked in the cassette stock unit, are taken out one by one from the cassette and conveyed for inspection to the plural wafer inspection units, respectively, by wafer conveyance means, and then they are conveyed successively, beginning with one that has been checked in any of the wafer inspection units, to the original cassette and are received therein.
In the latter publication No. Hei 5(1993)-136219, there is disclosed inspection equipment provided with plural inspection mechanisms and a probe card conveying mechanism, wherein inspection is carried out under successive loading and unloading of wafers with respect to the plural inspection mechanisms, and a predetermined probe card is conveyed and automatically loaded to each inspection mechanism by the probe card conveying mechanism in accordance with the type of wafer, thereby allowing inspection to be carried out.
Having studied the above techniques concerning wafer testing including a probe check, the present inventor has found the following facts.
For example, according to the technique disclosed in the former publication No. Hei 5(1993)-343497, plural cassettes and plural wafer inspection units are controlled in a centralized manner, so that many wafers received in a predetermined cassette are conveyed to an empty wafer inspection unit and checked therein, thereby shortening the inspection time required for each cassette. This technique is suitable mainly for limited item mass production, but is not considered suitable for multiple-item production. Particularly, no consideration is given in the publication to the application of the testing technique to a variety of items for each wafer inspection unit, nor is any consideration given to the replacement of test programs corresponding to various items.
According to the technique disclosed in the latter publication No. Hei 5(1993)-136219, a predetermined probe card is conveyed to each inspection mechanism in accordance with the type of wafer and inspection is carried out, whereby, in a multi-item low-volume production, the inspection of a wafer is also carried out efficiently so as to improve the production efficiency. In this technique, a correlation is specified between an inspection mechanism and a probe card in accordance with the type of wafer, and it is necessary to provide inspection mechanisms and probe cards in a number corresponding to the number of items, so that the scale of inspection equipment may become large. Besides, no consideration is given either to the application to a variety of items for each wafer inspection unit, or to the replacement of test programs corresponding to various items. Moreover, the wafer conveying unit used becomes larger in scale, giving rise to problems from the point of view of investment and space.
Further, in such a probe check, in the wafer testing step as referred to above, wafers are set into a prober in the unit of a lot, and a program is loaded to carry out a probe check. In this case, the lot is exchanged upon completion of one lot inspection; and, if a change of program is necessary for the new lot, a program is re-loaded manually to cope with a multi-item inspection. Since the inspection is thus carried out lot by lot, there are working loads, such as raising and lowering lots and changing program; besides, this imposes a wait on the worker, with consequent lowering of the working efficiency of the tester. Additionally, a maximum of twenty-five wafers can usually be received in one cassette, but in a multi-item production, there sometimes is a case where the number of items is one and the number of wafers is small. Since management is carried out in the unit of one lot and one cassette, the number of cassettes increases, leading to an increase of the working load and a lowering.of the working efficiency. One lot No. covers one fixed item or it may cover a plurality of items.
In view of the above-mentioned point, the present inventor has hit upon forming a network which covers probers, testers, manufacturing specification management, testing step control and test result management and modification of the probe software. As a result, a large-scale wafer conveying unit is not needed, and by the application to various items in the unit of a prober and by automatic replacement of test programs corresponding to various items, it becomes possible to reduce the working load during lot replacement and reduce the number of cassettes; and, it further becomes possible to realize a probe check for plural lots, which leads to improvement in the working efficiency of the testers.
It is an object of the present invention to provide a semiconductor integrated circuit device fabricating method and a testing method which, in a probe check in a wafer testing step, can reduce the working load and the waiting time of a worker during lot replacement, reduce the number of cassettes and improve the tester working efficiency, and which permits application to a variety of items in the unit of a prober.
The above and other objects and novel features of the present invention will become more apparent from the following description and the accompanying drawings.
Typical aspects of the invention, out of those disclosed herein, will be outlined below.
According to the present invention, for achieving the above-mentioned object, a network is formed, including probers, testers, manufacturing specification management, testing step control and test results management, and the prober""s software is modified, so that {circle around (1)} the manufacturing specification in a probe checking step is set under a unitary management (in terms of a data file) and manufacturing specification information in the probe check for each lot and each wafer in a cassette is fed to a tester, {circle around (2)} program selection, as well as a prober""s item parameter and measurement temperature, are controlled automatically in the tester on the basis of the manufacturing specification information in the probe check, {circle around (3)} the storage of probe check results to a storage medium (e.g. FD) is abolished in a test results acquiring network, and {circle around (4)} by modification of the prober""s software, a lot switching work is normally rendered automatic so as to reduce the working time and make the operation stop time zero, and the number of cassettes is reduced. There is no one-lot one-cassette limitation, with plural lots and plural items capable of being received in one cassette.
More specifically, in one aspect of the present invention, there is provided a semiconductor integrated circuit device fabricating method, including a wafer processing step of forming a predetermined integrated circuit on a wafer, a wafer testing step in which, after the end of processing of a predetermined cassette as one cassette out of plural cassettes, each accommodating the wafer with an integrated circuit formed thereon, the predetermined cassette is replaced with another cassette, and the wafer is subjected to an electrical characteristic test, and a product shipping step of shipping the wafer as a product, if it is judged to be non-defective as a result of the electrical characteristic test.
In another aspect of the present invention, there is provided a semiconductor integrated circuit device fabricating method wherein, as the wafer testing step, data of each lot and each wafer, in a cassette which accepts the item of the wafer with an integrated circuit formed thereon, are automatically replaced with a test program corresponding to each item in a unitarily managed state on a network with a representative lot No. as a key and the electrical characteristic test for the wafer is carried out; or, the same test is carried out while probe trace image data of a prober for the integrated circuit-formed wafer are checked off-line; or, when such wafers with the integrated circuit formed thereon are accommodated in plural items and plural lots into a cassette, an automatic change is made into test programs corresponding to the items, and the electrical characteristic test for the wafer is carried out.
In a further aspect of the present invention, there is provided a semiconductor integrated circuit device testing method, including a step of providing a wafer with a predetermined integrated circuit formed thereon, a step in which, after the end of processing of a predetermined cassette as one cassette out of plural cassettes, each accommodating the wafer with the integrated circuit formed thereon, the predetermined cassette is replaced with another cassette, and the wafer is subjected to an electrical characteristic test, and a step of shipping the wafer as a product, if it is judged to be non-defective as a result of the electrical characteristic test.
In a still further aspect of the present invention, there is provided a semiconductor integrated circuit device testing method wherein, as the step of carrying out the electrical characteristic test, data of each lot and each wafer, in a cassette which accepts the item of the wafer with the integrated circuit formed thereon, are automatically replaced with a test program corresponding to each item in a unitary managed state on a network with a representative lot No. as a key, and the electrical characteristic test for the wafer is carried out; or, the same test is carried out while probe trace image data of a prober for the integrated circuit-formed wafer are checked off-line; or, when such wafers with the integrated circuit formed thereon are accommodated in plural items and plural lots into a cassette, an automatic change is made into test programs corresponding to the items, and the electrical characteristic test for the wafer is carried out.